Single wafer rapid thermal processing ("RTP") is becoming a preferred technique in fabricating sub-half micron memory devices. This is primarily because RTP enables wafers to be heated rapidly at high temperatures using a controlled heating source. Nonetheless, high temperature processing methods for large diameter semiconductor wafers, such as RTP for example, as well as methods employing a furnace through a complete CMOS flow, have not eliminated the issue of thermal stress. Also, furnace annealing of wafers with high oxygen precipitation may substantially warp and/or bow during subsequent patterning and multi-step processing.
Transient heating techniques, such as laser annealing and RTP, are essentially non-equilibrium processes. In that light, large diameter silicon wafers typically warp and bow as a result of being subjected to high temperature or high stress films. This phenomenon is founded on the nonuniform coefficients of thermal expansion of the various materials which make up the wafer. Uniformly exposed to a high temperature, the wafer's edge reaches a substantially different temperature from the center of the wafer and different regions of the edge may acquire relatively different temperatures among themselves. These differences in temperature between the center of the wafer and its edges create a thermal stress over the wafer. At high temperature, this induced stress results in plastic deformation of the wafer, particularly where it exceeds the elastic limit of the silicon wafer itself.
As a by-product of thermal stress, high stress film deposition and patterning, a wafer will warp and bow where its elastic limit has been surpassed. A semiconductor substrate can deform, by means of warping and bowing, in a variety of ways.
The phenomenon of warp and bow typically results in the dislocation, slippage and gross mechanical instability of the wafer. These side effects of thermal stress can ultimately lead to reduction in device yield, dielectric defects, as well as reduced photolithographic yield. The reduced photolithographic yield is in part attributable to the degradation of wafer uniformity and flatness. Moreover, the loss of geometrical planarity of a wafer due to warp and bow substantially impacts the feasibility of processing a wafer, or leads to self-fracture of the wafer.
Both intrinsic and extrinsic stresses of the wafer, localized in a specific area or uniformly spread across its topography, impact on the flatness of the wafer. The wafer level distortion, in the form of a curve or pattern movement, translates into more stringent critical dimensions and overlay requirements at the lithography step level.
The phenomena of wafer warp and bow is further magnified in high density, sub-half micron devices because of their reliance on multilayer heterostructure formations. Each layer in these devices is typically associated with a different thermal expansion coefficient. Further, several masking steps are required to fabricate each layer, thus compounding component misalignment problems in the event of warp and/or bow type deformities. Thus, steady state exposure to high temperatures over a long period of time due to the effects of thermal stress encourages excessive warp and bow and loss of geometric planarity. Indeed, if the deformation is substantial, any further process venture may even break the wafer.
Representative examples of RTP apparatus may be found in U.S. Pat. Nos. 4,818,327, 5,155,336, 5,155,337, 5,418,885 and 5,444,815. Each disclose RTP apparatus including an RTP chamber having a lamp assembly comprised of a plurality of heating lamps. In U.S. Pat. Nos. 4,818,327 and 5,155,337 the plurality of heating lamps are simultaneously controlled, whereas in the other patents the several lamps are individually controlled. A theme common to each of these patent disclosures is the intent to maintain a semiconductor wafer at a uniform temperature during processing to promote objects such as uniform layer deposition, patterning and the like. It is even suggested in U.S. Pat. Nos. 4,818,327 and 5,155,336 that obtaining temperature uniformity in the substrate during temperature cycling of the substrate is necessary to prevent thermal stress-induced damage such as warpage.
Yet, regardless of how sophisticated past attempts at maintaining a semiconductor structure at a uniform temperature during RTP to minimize warpage may have been, none have proven completely successful. Consequently, the very act of RTP treatment of a substrate imparts some unavoidable measure of deformation to the substrate. Further, as mentioned above, such deformation may be exacerbated by other localized or generalized intrinsic and extrinsic stresses acting upon the wafer.
U.S. Pat. No. 5,382,551 has proposed an effective method to reduce the effects of semiconductor structural deformities. That technique involves depositing at least one layer superjacent and at least one layer subjacent a semiconductor substrate. The substrate may be deformed, such as by warp, bow, or both, either inherently or as a result of the layers deposited thereabove and therebelow. The layers may be deposited using any conventional processes known to those skilled in the art. For example, the layers may be deposited by at least one of Low Pressure Chemical Vapor Deposition ("LPCVD"), Plasma Deposition, and Rapid Thermal Processing Chemical Vapor Deposition ("RTPCVD"), or by other means known in the art.
The deformed substrate is then examined for warp and bow, and the warp and bow of the deformed substrate is compared with a reference. Thereafter, the thickness of at least one of the superjacent and subjacent layers is reduced, or at least one of the subjacent layer(s) is removed (possibly in combination with reducing the thickness of the superjacent layer) to reduce the deformity until the wafer planarity corresponds substantially to that of the reference.
Although this method is a reliable means by which to achieve wafer planarity, it contributes additional layer reduction/removal steps to the semiconductor device fabrication process and may detrimentally affect the superjacent or circuit bearing side of the wafer. Moreover, removal of material from the wafer also increases the possibility of contamination effects that may result in wafer rejection, thereby reducing throughput productivity.
A need exists, therefore, for an uncomplicated semiconductor shape correction method which utilizes a minimum of procedural steps to minimize semiconductor structural deformities.